--
-- VHDL Architecture Fietscomputer_lib.t_ff.v
--
-- Created:
--          by - jcmooije.UNKNOWN (dtp6241)
--          at - 08:38:47 10-06-2009
--
-- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY t_ff IS
   PORT( 
      t   : IN     std_logic;
      clk : IN     std_logic;
      rst : IN     std_logic;
      q   : OUT    std_logic
   );

END ENTITY t_ff;

--
ARCHITECTURE v OF t_ff IS
BEGIN
  
    PROCESS(rst, clk)
        BEGIN
          IF rst = '1' THEN
            q <=  '0';
          ELSIF RISING_EDGE(clk) THEN
                     
            q <= t XOR q;
                    
          END IF;
        END PROCESS;
  
  
  
END ARCHITECTURE v;

